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  • 期刊名称:

    Microprocessors and microsystems

  • 中文名称: 微处理器和微系统
  • 刊频: 0.516
  • ISSN: 0141-9331
  • 出版社: -
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1643条结果
  • 机译 基于量子点细胞自动机的纳米仲裁器设计与仿真
    摘要: Arbiters are the essential components of the Network-On-Chip (NOC) systems and are used to resolve the contention problem where multiple requests must be handled for shared resources. On the other hand, with the ever-increasing downsizing trend in the fabrication technology, Quantum-dot Cellular Automata (QCA) with its nano scales and very low power consumption is a promising candidate for implementing future NOCs. In the current work, we design and simulate nano-arbiters using QCA with the following contributions: i) The 2-bit Basic Round Robin Arbiter (RRA) and the 2-bit Ping Pong Arbiter (PPA) are designed and simulated; ii) A solution for an erroneous condition found in the original circuit of RRA is reported and fixed; iii) We use Cartesian Genetic Programming (CGP) approach to simplify the RRA and PPA designs; iv) In order to leverage our QCA designs, we apply a more realistic clock distribution (2-DW clocking) and report the results. At the end, a one-to-one comparison of the two arbiters designed with QCA will be presented using such benchmarks as area, latency, etc. Our results show that in the 2-bit input mode, the PPA arbiter has the best overall performance. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 安全关键型嵌入式系统的双模型方法
    摘要: The paper presents the design of digital controllers based on two models: the Petri net model, and the UML state machine. These two approaches differ in many aspects of design flow, such as conceptual modelling, and analysis and synthesis. Each of these approaches can be used individually to design an efficient logic controller, and such solutions are well-known, but their interoperability can contribute to a much better understanding of logic controller design and validation. This is especially important in the case of safety- or life-critical embedded systems, and apart from this, a dual-model controller design can make up redundant system increasing its reliability. (C) 2019 Published by Elsevier B.V.
  • 机译 轻量级实现SILC,CLOC,AES-JAMBU和COLM认证密码
    摘要: Authenticated encryption schemes provide both confidentiality and integrity services, simultaneously. CAESAR competition will identify a portfolio of authenticated ciphers, which is expected to be suitable for widespread adoption and offers advantages over AES-GCM. An important criterion for selecting the final candidates, besides security, is the hardware performance in resource-limited environments. In this paper, SILC, CLOC, AES-JAMBU, and COLM authenticated ciphers have been selected from the third round of the CAESAR competition for hardware evaluation. The main reasons to choose these schemes are their lightweight design, sufficient security level, and the use of the AES algorithm as their underlying block cipher. To the best our knowledge, it is the first time that an 8-bit lightweight architecture which is compatible with API v2 is presented for the selected schemes. To implement AES, the Atomic-AES v2 which is one of the smallest implementations has been adopted according to the requirements of the selected schemes. Furthermore, to reduce the area in the hardware implementation, several techniques are used, including implementing one AES core in the datapath, sharing registers to store intermediate values, implementing the tweak functions with the shuffling of wires, and implementing doubling on the GF(2128) with 8-bit architecture to construct the higher-order multipliers. The implementation results are presented on ASIC and FPGA platforms. The proposed architecture for each scheme on the two platforms is similar, but different optimization techniques are used for each platform, e.g. the AES S-box is implemented as ROM-based and logic-based on FPGA and ASIC, respectively. The comparing of the results with 128-bit implementations shows that the area on FPGA and ASIC is reduced up to 65% and 88%, respectively. The results of the current study demonstrate that AES-JAMBU has the lowest hardware area and the highest throughput and performance on both platforms. Besides, CLOC has the highest area reduction on both platforms, compared with those of the 128-bit implementations. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 用于尺度不变特征变换关键点描述符匹配的全流水线FPGA加速器
    摘要: The scale invariant feature transform (SIFT) algorithm is considered a classical feature extraction algorithm within the field of computer vision. SIFT keypoint descriptor matching is a computationally intensive process due to the amount of data consumed. In this work, we designed a novel fully pipelined hardware accelerator architecture for SIFT keypoint descriptor matching. The accelerator core was implemented and tested on a field programmable gate array (FPGA). The proposed hardware architecture is able to properly handle the memory bandwidth necessary for a fully-pipelined implementation and hits the roofline performance model, achieving the potential maximum throughput. The fully pipelined matching architecture was designed based on the consine angle distance method. Our architecture was optimized for 16-bit fixed-point operations and implemented on hardware using a Xilinx Zynq-based FPGA development board. Our proposed architecture shows a noticeable reduction of area resources compared with its counterparts in literature, while maintaining high throughput by alleviating memory bandwidth restrictions. The results show a reduction in consumed device resources of up to 91% in LUTs and 79% of BRAMs. Our hardware implementation is 15.7 x faster than the comparable software approach. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 在异构多核边缘设备上使用压缩传感进行实时心电图监测
    摘要: In a typical ambulatory health monitoring systems, wearable medical sensors are deployed on the human body to continuously collect and transmit physiological signals to a nearby gateway that forward the measured data to the cloud-based healthcare platform. However, this model often fails to respect the strict requirements of healthcare systems. Wearable medical sensors are very limited in terms of battery lifetime, in addition, the system reliance on a cloud makes it vulnerable to connectivity and latency issues. Compressive sensing (CS) theory has been widely deployed in electrocardiogramme ECG monitoring application to optimize the wearable sensors power consumption. The proposed solution in this paper aims to tackle these limitations by empowering a gateway-centric connected health solution, where the most power consuming tasks are performed locally on a multicore processor. This paper explores the efficiency of real-time CS-based recovery of ECG signals on an IoT-gateway embedded with ARM's big.LITTLE (TM) multicore for different signal dimension and allocated computational resources. Experimental results show that the gateway is able to reconstruct ECG signals in real-time. Moreover, it demonstrates that using a high number of cores speeds up the execution time and it further optimizes energy consumption. The paper identifies the best configurations of resource allocation that provides the optimal performance. The paper concludes that multicore processors have the computational capacity and energy efficiency to promote gateway-centric solution rather than cloud-centric platforms. (C) 2019 Published by Elsevier B.V.
  • 机译 用于液位过程的非线性相互作用耦合球罐系统的新型模糊分数阶PID控制器
    摘要: In this paper, a novel Fuzzy Fractional Order Proportional Integral Derivative (FFOPID) controller is proposed to control the liquid level of Two Tank Spherical Interacting System (TTSIS). Spherical tanks are widely used in process industries due to its high storage capacity. These are non-linear due to its varying surface area with respect to its height and hence the level control of a spherical tank system is a challenging task. Fractional Order Proportional Integral Derivative (FOPID) controller is designed for a liquid level control of a spherical tank which is modelled as a fractional Order System. The performance indices such as rise time, settling time, peak time and peak overshoot are analysed for the proposed control scheme and compared to conventional controllers such as PI, PID, PID-SMC, FOPID. Moreover the time integral performance measures such as ITAE, IAE and ISE are analysed. Experimental results are shown to validate the obtained results with those of simulations. It has been proven that FFOPID outperforms all other existing techniques in terms of various time domain specifications and time integral performance measures. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 感应耦合医疗植入物中无线数据流的弹性流控制
    摘要: This paper describes the hardware implementation of a custom communication protocol tailored for low power telemetry data streaming over an inductive link. An efficient transceiver design is achieved by adapting only the essential physical layer features of a typical RFID baseband processor and optimizing the flow control logic for continuous and reliable data transfer. For the external near-field reader, we provide a logical model for receiver operation and suggest a simple forward error correction (FEC) mechanism. The benefit of FEC in the context of developed communication system is demonstrated by simulations, and projections of design scalability are also presented. The proposed communication system was implemented in 28nm CMOS process. Place-and-route (PNR) results occupy only 0.0048 mm(2) of core area, and the transient simulations show a power consumption of 306 nW at 0.5 V supply and a master clock of 845.7 kHz. The implementation provides an uplink rate of 12 kbit/s, sufficient for reliable transmission of a 1-channel 1 kS/s 12-bit sample recording. (C) 2019 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license. (http://creativecommons.org/licenses/by-nc-nd/4.0/)
  • 机译 定制处理器,用于与协议无关的数据包解析
    摘要: Networking devices such as switches and routers have traditionally had fixed functionality. They have the logic for the union of network protocols matching the application and market segment for which they have been designed. Possibility of adding new functionality is limited. One of the aims of Software Defined Networking is to make packet processing devices programmable. This provides for innovation and rapid deployment of novel networking protocols. The first step in processing of packets is packet parsing. In this paper, we present a custom processor for packet parsing. The parser is protocol-independent and can be programmed to parse any sequence of headers. It does so without the use of a Ternary Content Addressable Memory. As a result, the area and power consumption are noticeably smaller than in the state of the art. Moreover, its output is the same as that of the parser used in the Reconfigurable Match Tables (RMT). With an area no more than that of parsers in the RMT architecture, it sustains aggregate throughput of 3.4 Tbps in the worst case which is an improvement by a factor of 5. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 专用异构多处理器系统的基于SystemC的电子系统级设计空间探索环境
    摘要: This work faces the problem of the Electronic System-Level (ESL) HW/SW co-design of dedicated electronic digital systems based on heterogeneous multi-processor architectures. In particular, the work presents a prototype SystemC-based environment that exploits a Design Space Exploration (DSE) approach able to suggest an HW/SW partitioning of the system specification and a mapping onto an automatically defined architecture. The descriptions of the reference HW/SW co-design methodology and the main design issues related to the developed DSE SW tools, supported by two reference use cases that allows to understand the role of the DSE step in the whole design flow, represent the core of the paper. (C) 2019 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY license. (http://creativecommons.org/licenses/by/4.0/)
  • 机译 低功耗单精度BCD浮点吠陀乘法器
    摘要: In this paper, the Binary coded decimal floating-point multiplier (BCD-FPM) and Binary floating-point multiplier (BFPM) with binary to BCD (B2BCD) converter are proposed using Urdhva-Tiryakbhyam (UT) sutra. Two methods are proposed for BCD-FPM and comparison is made between BCD-FPM and BFPM with B2BCD converter. The designs are modelled in Verilog HDL and synthesized based on the 90nm standard cell library in Cadence EDA Tool. Comparisons are based on the synthesis report generated by Cadence RTL complier and implemented in Encounter RTL TO GDSII system. The results show that BCD-FPM has better performance in terms of delay and power. The power for Method II gets reduced by 59.47% and 73.40% when compared with Method I and BFPM with B2BCD converter respectively. The delay for Method II gets reduced by 6.9% than Method I and 30.37% than BFPM with B2BCD converter. The pipelined architecture is designed for Method II as it is efficient than other multipliers, whose delay is reduced by 65.82% after pipelining. (C) 2019 Published by Elsevier B.V.
  • 机译 基于修改的动态电流模式逻辑的LFSR,适用于低功耗应用
    摘要: Shift Register, which is a cascade of flip flops shares the same clock and the outputs are connected to the data input of the next one in the chain. Linear-feedback shift register or shortly LFSR is one such shift register whose input is a linear function of its previous state. Exclusive-OR (XOR) is the most commonly used linear function. LFSR's help in generating pseudo-random numbers, fast digital counters, pseudo-noise sequences and whitening sequences. LFSR's can be realised both using hardware and software. When it comes to hardware implementation, MOS current mode logic (MCML) method can be used for designing the LFSR. There are lots of drawbacks with the traditional MCML method including the static power dissipation, more power consumption at low frequencies as compared with CMOS circuits, inappropriate for large systems involving power-down modes and it's not a cost effective solution either. To overcome these issues and to achieve the high speed characteristics of MCML, we present the modified dynamic current mode logic and is a good solution for battery powered systems and portable solutions. Our simulation results also confirm the same where a 16 bit adder circuit fabricated using CMOS technology has only a delay of 1.22 ns and dissipates 19.0 mW at 400 MHz. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 磁共振图像中辐射剂量计算的脑肿瘤分类和检测优化技术
    摘要: The tumor cell leads brain to abnormal growth birth. The Brain Tumors (BT) leads to damage or affected brain if it is not predicted early stage and rectified properly with proper treatment. The proper treatment as advised by the physician need to be followed based on the size of the tumor and its position. The accurate finding of tumor position and size is the difficult task. In recent years to structures of the body in internal position had seen detailed, the Magnetic Resonance (MR) technique if the radiology used in medical imaging. This paper describes a novel approach for BT MLTS-HSO segmentation and extracts the features then classified with different classifiers (KNN, DSVM, NB, and RBFN) for MR BT images. The present approach is SVM, NN, and ANFIS where the seed point is selected on a scale based and detected the tumor region and also compute the performance metrics and radiation dosage. Thus the proposed system is the ability of the calculate size and position of the tumor. It has more accurate prediction of the required surgery and other therapy procedures. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 独立光伏系统新控制技术的设计与开发
    摘要: A Sub-Maximum Power Point Tracking (S-MPPT) algorithm improves the performance of Photo Voltaic (PV) systems. This S-MPPT is used in single-phase PV system to test the tracking accuracy and its impact on the consistency of the whole system. Single phase PV Deadbeat Scheduler is proposed in this paper. The Deadbeat scheduler is a linear system. It initializes each initial state of the system to zero in shortest time possible. A single phase PV structure configuration is proposed to decrease the partial shading effect by changing the parameters of S-MPPT control algorithm. Thus, voltage sensor based S-MPPT algorithm through voltage reference control technique with the help of controller is developed for minimizing the tracking time and steady state oscillations. Selection of the objective function to mitigate the drawbacks associated with voltage sensor based algorithm for a decrease in solar irradiance are also demonstrated. The proposed MPPT algorithm with the designed controller is tested for a step change in irradiance from 270 to 480 W/m2 with a perturbation time of 20 ms and Delta V = 0.5V (perturbation of voltage). From the simulation results, the proposed method with S-MPPT plus deadbeat control algorithm is compared with other existing algorithms. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 Pods-用于物联网环境中多核嵌入式架构的新型智能节能和动态频率缩放
    摘要: In the Advent of the Internet of Things (IoT), embedded architecture takes an important dimension in terms of energy and accomplishment. The embedded system needs more and more intelligent algorithms for better performance and energy efficiency to fit into an IoT scenario. Moreover, with the existence of high-performance multi-core embedded architectures, achievements of energy efficiency remains in the dark side of the research. Several algorithms such as dynamic frequency scaling, thread mapping, starvation methodologies were proposed in embedded architectures for efficient usages of clock frequencies and these features were used as the energy saving modes in which the consumption of energy in the embedded architectures are being controlled. But these methods have several backlogs which permits the use of consumption in the embedded architectures. Considering the above features, this paper proposes a new methodology PODS(Predictors for Optimized Dynamic Scaling) which integrates a powerful machine learning algorithm for scaling the clock frequencies by the input workloads and allocation of the core depending based on the workload. The proposed framework PODS has different phases of working namely workload extraction, characterization, and optimization using BAT algorithms and prediction extreme Machine - Learning. The algorithm was tested on ARM/Cortex architectures (Raspberry Pi 3 Model B+), an evaluated algorithm using the IoMT benchmarks and various parameters that include energy consumption, accuracy of detection/prediction was determined and analyzed. It is found that the implementation of the proposed framework in the test is seen resulting between 35 and 40% reduction in the consumption of the power. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 容错图像处理的近似加法器和乘法器的设计
    摘要: An adder is the basic computational circuit in digital Very Large Scale Integration (VLSI) design. To improve the design metrics of an adder, Approximate Adders (AAs) have been proposed. These adders have been applied and analyzed on 8 x 8 Dadda multipliers (DMs). The design metrics of proposed AAs, Approximate Dadda Multipliers (ADMs) are synthesized in Cadence Register-Transfer Level (RTL) compiler and compares the design metrics with three different technology nodes. The quantitative characterization such as Error Distance (ED), Error Rate (ER), Pass Rate (PR), Mean Error Distance (MED), Normalised Error Distance (NED) of AAs, and ADMs are computed. Image blending and sharpening approaches have been applied using AAs, and approximate multipliers respectively to analyse the image quality metric using the proposed approximate framework. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 用于3GPP-LTE NB-IoT设备的区域高效加密处理器的设计
    摘要: Providing information security is crucial for the Internet of Things (IoT) devices, platforms in which the available power budget is very limited. This paper tackles this challenge and presents a cryptographic processor compliant with the security algorithms specified by the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) NarrowBand IoT (NB-IoT) standard. The proposed processor has been optimized to the needs of the low end portfolio technologies that compose the IoT market, which addresses low-area, low-cost and low-data rate applications. Operation analysis at the algorithm-level and hardware sharing at the architecture-level have enabled extensive area reduction. The cryptographic processor has been described using the High-Level Synthesis (HLS) design flow and integrated with a general purpose processor in a cycle accurate virtual platform. The design achieves a reduction of area ranging from 5% to 42% in comparison to similar work. Synthesis results using a 65-nm CMOS technology show that the processor has a hardware cost of 53.6 kGE, and is capable of performing at 52.4Mbps for the block cipher and 800Mbps for the stream cipher algorithms at a 100 MHz clock. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 利用多功能生态平衡控制技术提高太阳能蒸发冷却器的性能
    摘要: Solar Energy is one of the essential sources of sustainable power source. Solar Photovoltaic power (SPV) is utilized today in various applications. The mechanical load of the current evaporative cooler is the primary source of high energy consumption. This case incited us to look for better approaches to enhance the evaporative cooler regards to energy production, water utilizes proficiency, life, support, and reliance on utility power. Thus, we planned, built, and tried another computerized solar-powered evaporative cooler that significantly enhances existing outlines on every one of the regions specified above utilizing Versatile Ecological Balanced Control (VEBC) algorithm. Evaporative cooling is a notable framework to be a productive and economical means for decreasing the temperature and expanding the relative humidity in a nook. The test comes about because of the altered cooler in light of the new plan demonstrate that it conveyed air with recognizably higher humidity and lower temperature than the standard outline. The test comes about because of the changed cooler given the first model demonstrate that it furnished a climate with discernibly higher humidity and lower temperature than the traditional design. The proposed VEBC strategy decreases the storage temperature yet, also, builds the relative humidity of the storage which is essential for keeping up the freshness of the items. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 迈向协作式智能物联网eHealth:从设备到雾化和云化
    摘要: The relationship between technology and healthcare due to the rise of intelligent Internet of Things (IoT), Artificial Intelligence (AI), and the rapid public embracement of medical-grade wearables has been dramatically transformed in the past few years. AI-powered IoT enabled disruptive changes and unique opportunities to the healthcare industry through personalized services, tailored content, improved availability and accessibility, and cost-effective delivery. Despite these exciting advancements in the transition from clinic-centric to patient-centric healthcare, many challenges still need to be tackled. The key to successfully unlock and enable this horizon shift is adopting hierarchical and collaborative architectures to provide a high level of quality in key attributes such as latency, availability, and real-time analytics. In this paper, we propose a holistic AI-driven IoT eHealth architecture based on the concept of Collaborative Machine Learning approach in which the intelligence is distributed across Device layer, Edge/Fog layer, and Cloud layer. This solution enables healthcare professionals to continuously monitor health-related data of subjects anywhere at any time and provide real-time actionable insights which ultimately improves the decision-making power. The feasibility of such architecture is investigated using a comprehensive ECG-based arrhythmia detection case study. This illustrative example discusses and addresses all important aspects of the proposed architecture from design implications such as corresponding overheads, energy consumption, latency, and performance, to mapping and deploying advanced machine learning techniques (e.g., Convolutional Neural Network) to such architecture. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 基于雾云的网络物理系统,用于溃疡性结肠炎的诊断以及阶段分类和管理
    摘要: Ulcerative Colitis is a fairly common, chronic or long-term disease that causes inflammation of the large intestine. It can be debilitating and can sometimes lead to life threatening complications. Therefore, its diagnosis in nascent stages is important. Healthcare services based on Fog-Cloud assisted Cyber-Physical Systems are emerging as a proactive and efficacious solution to provide remote monitoring of individuals for early detection and consequent management of several diseases. This paper presents a novel IoT-Fog-Cloud assisted Cyber Physical System for diagnosis and stage classification of Ulcerative Colitis using Naive Bayes classifier and Deep Neural Network respectively. A vital point of this paper is real-time alert generation from Fog Layer in case the user need emergency treatment if he/she is already diagnosed with UC. Finally, analysis results and compiled medical information of each user is stored on cloud. Implementation results of the proposed framework proves its efficiency in diagnosis and subsequent stage classification of Ulcerative Colitis with real-time classification mechanism at fog layer. Furthermore, alert generation improves the efficacy of the proposed system. (C) 2019 Elsevier B.V. All rights reserved.
  • 机译 混合主内存上的超级交换内存利用率可改善任务执行并降低功耗
    摘要: The problem of lifetime maximization of PCM has been well studied. The arrival of non-volatile memory devices has replaced the traditional DRAM. Still the DRAM has many limitations on endurance and high power write operations. Similarly, number of designs has been discussed earlier to maximize the lifetime of PCM by catching the main memory at available DRAM. Still they could not achieve the performance on power consumption reduction and increasing memory utilization. To improve the performance in power consumption reduction and lifetime maximization, and categorical model is presented in this paper. The proposed method categorizes the processes according to their memory access activity. The categorized process has been allocated to respective part of hybrid memory which encourages maximum read and minimum write in PCM. The proposed method increases the lifetime of PCM than other methods. (C) 2019 Elsevier B.V. All rights reserved.
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